Semiconductor devices may be coupled to various external devices to perform certain functions. The external devices provide appropriate signals (e.g., clock signals, data signals, etc.) to enable the semiconductor device to operate. The operational frequency of the semiconductor devices are usually quite significant. However, certain circumstances may arise where the external device is incapable of providing clock signals at the operational frequency of the semiconductor device. For example, this may occur during testing of semiconductor devices. The testing is typically performed by a test platform that provides test signals to the semiconductor devices under test. The operational frequency of the semiconductor devices under test are usually quite significant. However, the maximum clock frequency attainable during the test is limited by the particular test platform being utilized, where the test platforms provide clock signals at frequencies below the operational frequencies of the devices under test. Thus, the semiconductor devices may be tested under conditions different than the device operational conditions.
In addition, other external devices or platforms (e.g., memory controller, etc.) coupled to the semiconductor devices may similarly provide clock signals at frequencies below the operational frequencies of the device, thereby degrading semiconductor device performance.
Attempts have been made to address the aforementioned problem. For example, a high speed platform may be utilized in conjunction with the semiconductor device. Further, hardware may be added to a platform to double the platform clock frequency, or a specific mode may be employed that doubles the external clock provided to the semiconductor devices.
However, these approaches suffer from several disadvantages. In particular, the high speed platforms tend to be extremely expensive and include limitations (e.g., with respect to parallel testing and signal integrity). Although the hardware and mode described above enable the clock frequency of the platform and external clock to be doubled, there is no mechanism to provide for doubling of the data rate. In other words, even though the clock frequency is increased, the data rate remains the same. For example, a test for a semiconductor memory device may include writing a toggling data sequence to memory (where the data toggles with each transition of a test system clock signal) in order to simulate stress on the device during operational conditions. Since the data or toggling rate is based on the test system clock frequency, the toggling rate of the data remains the same despite the increased clock frequency as described above, thereby providing incompatibility with the increased clock signal and insufficient coverage for the test.